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Rev 0; 1/08
High-Voltage, NV, I2C POT
General Description
The DS3502 is a 7-bit, nonvolatile (NV) digital potentiometer (POT) featuring an output voltage range of up to 15.5V. Programming is accomplished by an I2C-compatible interface, which can operate at speeds of up to 400kHz. External voltages are applied at the RL and RH inputs to define the lowest and highest potentiometer outputs. 128 Wiper Tap Points Full-Scale Resistance: 10k I2C-Compatible Serial Interface
Features
DS3502
Address Pins Allow Up to Four DS3502s to Share the Same I2C Bus Digital Operating Voltage: 2.5V to 5.5V Analog Operating Voltage: 4.5V to 15.5V Operating Temperature: -40C to +100C 10-Pin SOP Package
Applications
TFT-LCD VCOM Calibration Instrumentation and Industrial Controls Mechanical POT Replacement
Ordering Information
PART DS3502U+ TEMP RANGE -40C to +100C -40C to +100C PIN-PACKAGE 10 SOP 10 SOP
Pin Configuration and Typical Operating Circuit appear at end of data sheet.
DS3502U+T&R
+Denotes a lead-free package. T&R = Tape and reel.
Functional Diagram
RH 127 SDA SCL 7-BIT WIPER REGISTER 126
DS3502
125
DECODER LEVEL SHIFTER 7-BIT NONVOLATILE MEMORY 2
1
0 CONTROL CIRCUITRY AND ADDRESS DECODE
A1 A0
RL RW
________________________________________________________________ Maxim Integrated Products
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High-Voltage, NV, I2C POT DS3502
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Relative to GND ...............-0.5V to +6.0V Voltage Range on V+ Relative to GND ..................-0.5V to +17V Voltage Range on SDA, SCL, A0, A1 Relative to GND.......-0.5V to (VCC + 0.5V), not to exceed 6.0V Voltage Range on RH, RL, RW...................................-0.5V to V+ Voltage Range Across RH and RL Pins .....................-0.5V to V+ Operating Temperature Range .........................-40C to +100C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. Maximum RW Current ...........................................................1mA
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +100C)
PARAMETER Supply Voltage V+ Voltage Input Logic 1 (SCL, SDA, A0, A1) Input Logic 0 (SCL, SDA, A0, A1) Resistor Inputs (RL, RW, RH) Wiper Current SYMBOL VCC V+ VIH VIL VRES IWIPER (Note 1) V+ > VCC CONDITIONS MIN +2.5 +4.5 0.7 x VCC -0.3 -0.3 TYP MAX +5.5 +15.5 VCC + 0.3 0.3 x VCC +15.5 1 UNITS V V V V V mA
ELECTRICAL CHARACTERISTICS
(VCC = +2.5V to +5.5V, TA = -40C to +100C, unless otherwise noted.)
PARAMETER VCC Supply Current Standby Supply Current V+ Bias Current Input Leakage (SDA, SCL, A0, A1) Wiper Response Time Low-Level Output Voltage (SDA) I/O Capacitance Power-Up Recall Voltage Power-Up Memory Recall Delay Wiper Resistance End-to-End Resistance (RH to RL) RTOTAL Tolerance CH, CL, CW Capacitance CPOT SYMBOL ICC I STBY I V+ IL tWRS VOL CI/O VPOR tD RW RTOTAL TA = +25C -20 10 (Note 4) (Note 5) V+ = 15.0V 10 +20 1.2 3mA sink current 0.0 5 -1 (Note 2) (Note 3) CONDITIONS MIN TYP 0.2 MAX 3 10 +1 +1 1 0.4 10 2.6 3 5000 k % pF UNITS mA A A A s V pF V ms
2
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High-Voltage, NV, I2C POT
VOLTAGE-DIVIDER CHARACTERISTICS
(VCC = +2.5V to +5.5V, TA = -40C to +100C, unless otherwise noted.)
PARAMETER Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Full-Scale Error Ratiometric Temp Coefficient SYMBOL INL DNL ZSERROR FSERROR TCV (Note 6) (Note 7) V+ = 4.5V (Note 8) V+ = 4.5V (Note 9) WR/IVR register set to 40h CONDITIONS MIN -1 -0.5 0 -2 0.5 -1 4 TYP MAX +1 +0.5 2 0 UNITS LSB LSB LSB LSB ppm/C
DS3502
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.5V to +5.5V, TA = -40C to +100C, timing referenced to VIL(MAX) and VIH(MIN). See Figure 2.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading EEPROM Write Time Pulse-Width Suppression Time at SDA and SCL Inputs A0, A1 Setup Time A0, A1 Hold Time SDA and SCL Input Buffer Hysteresis SYMBOL f SCL tBUF tHD:STA tLOW tHIGH tHD:DAT t SU:DAT t SU:STA tR tF t SU:STO CB tW t IN t SU:A tHD:A (Note 11) (Note 12) (Note 13) Before START After STOP 0.6 0.6 0.05 x VCC 10 50 (Note 11) (Note 11) (Note 10) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms ns s s V
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High-Voltage, NV, I2C POT DS3502
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.5V to +5.5V)
PARAMETER EEPROM Write Cycles SYMBOL TA = +70C TA = +25C CONDITIONS MIN 50,000 200,000 TYP MAX UNITS Writes
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Note 7:
Note 8: Note 9: Note 10: Note 11: Note 12: Note 13:
All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative. ICC is specified with the following conditions: SCL = 400kHz, SDA pulled up, and RL, RW, RH floating. ISTBY is specified with SDA = SCL = VCC = 5.5V and resistor pins floating. This is the minimum VCC voltage that causes NV memory to be recalled. This is the time from VCC > VPOR until initial memory recall is complete. Integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resistor setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. INL = [V(RW)i - (V(RW)0]/LSB(ideal) - i, for i = 0...127. Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position. DNL = [V(RW)i+1 - (V(RW)i]/LSB(ideal) - 1, for i = 0...126. ZS error = code 0 wiper voltage divided by one LSB (ideal). FS error = (code 127 wiper voltage - V+) divided by one LSB (ideal). I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode timing. CB--total capacitance of one bus line in picofarads. EEPROM write time begins after a STOP condition occurs. Pulses narrower than max are suppressed.
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High-Voltage, NV, I2C POT
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
1.6 SUPPLY CURRENT (A) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 1.0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) SDA = SCL = VCC, V+ = 15.5V RW, RH, AND RL ARE FLOATING
DS3502 toc01
DS3502
SUPPLY CURRENT vs. TEMPERATURE
DS3502 toc02
1.8
1.5
1.4 SUPPLY CURRENT (A)
1.3
1.2
1.1 SDA = SCL = VCC = 5V, V+ = 15.5V RW, RH, AND RL ARE FLOATING
INTEGRAL NONLINEARITY vs. POTENTIOMETER SETTING
DS3502 toc03
DIFFERENTIAL NONLINEARITY vs. POTENTIOMETER SETTING
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
DS3502 toc04
1.0 0.8 INTEGRAL NONLINEARITY (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 20 40 60 80 100 120 POTENTIOMETER SETTING (DEC)
0.5 DIFFERENTIAL NONLINEARITY (LSB)
0
20
40
60
80
100
120
POTENTIOMETER SETTING (DEC)
Pin Description
NAME SDA GND VCC A1, A0 RH RW RL V+ SCL PIN 1 2 3 4, 5 6 7 8 9 10 I2C Serial Data. Input/output for I2C data. Ground Terminal Supply Voltage Terminal Address Select Inputs. Determines I2C slave address. Slave address is 01010A1 A0X. (See the Slave Address Byte and Address Pins section for details). High Terminal of Potentiometer Wiper Terminal of Potentiometer Low Terminal of Potentiometer Wiper Bias Voltage I2C Serial Clock. Input for I2C clock. FUNCTION
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High-Voltage, NV, I2C POT DS3502
Simplified Functional Diagram
V+ VCC GND RH
DS3502
SCL I2C INTERFACE CONTROL LOGIC/ REGISTER (02h)
POS 7Fh
SDA
MODE BIT
A0
WIPER REGISTER/ INITIAL VALUE REGISTER (WR/IVR)
RW
A1
00h POS 00h RL
Detailed Description
The DS3502 contains a single potentiometer whose wiper position is controlled by the value in the Wiper Register (WR). The initial power-up value of the wiper position is set by programming the Initial Value Register (IVR). On power-up, the data stored in the IVR register is loaded into the WR register, which sets the position of the potentiometer's wiper.
Regardless of the setting of the MODE bit, all I2C reads of address 00h return the contents of the WR register. Setting MODE = 1 allows for quick writing of SRAM without the added delay of writing to the associated EEPROM register. The data that is stored in EEPROM and SRAM remains unchanged if the MODE bit is toggled. The volatile CR register powers up as 00h, setting the device into MODE = 0.
Control Register
The Control Register (CR) located in register 02h contains the WR/IVR Address Mode bit (MODE bit). The MODE bit determines how I2C data is written to the WR and IVR data register as follows: MODE = 0: I2C writes to memory address 00h write to (CR = 00h) both WR and IVR. I2C reads from address 00h read from WR. MODE = 1: I2C writes to memory address 00h write to (CR = 80h) WR. I2C reads from address 00h read from WR.
Digital Potentiometer Output
The potentiometer consists of 127 resistors in series connected between the RH and RL pins. Between each resistance and at the two endpoints, RH and RL, solidstate switches enable RW to be connected within the resistive network. The wiper position and the output on RW are decoded based on the value in WR. If RH, RL, and RW are externally connected in a voltage-divider configuration, then the voltage on RW can be easily calculated using the following equation: VRW = VRL + WR (V - VRL ) 127 RH
where WR is the wiper position in decimal (0-127).
Table 1. Memory Map
REGISTER WR/IVR CR NAME Wiper Register/Initial Value Register Control Register ADDRESS (HEX) 00 02 FACTORY/POWER-UP DEFAULT (HEX) 40 00 (Mode 0)
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High-Voltage, NV, I2C POT
Slave Address Byte and Address Pins
The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 1). The DS3502's slave address is determined by the state of the A0 and A1 address pins. These pins allow up to four devices to reside on the same I2C bus. Address pins tied to GND result in a 0 in the corresponding bit position in the slave address. Conversely, address pins tied to VCC result in a 1 in the corresponding bit positions. For example, the DS3502's slave address byte is 50h when A0 and A1 pins are grounded. I2C communication is described in detail in the I 2 C Serial Interface Description section.
MSB 0 1 0 1 0 A1 A0 LSB R/W
Slave devices: Slave devices send and receive data at the master's request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. STOP condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTS are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the
DS3502
SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1.
Figure 1. DS3502 Slave Address Byte
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. (See Figure 2 and the I2C AC Electrical Characteristics table for additional information.) Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions.
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 2. I2C Timing Diagram
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High-Voltage, NV, I2C POT
data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by transmitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data. Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave address byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The slave address byte of the DS3502 is shown in Figure 1. When the R/W bit is 0 (such as in 50h), the master is indicating it will write data to the slave. If R/W = 1 (51h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS3502 assumes the master is communicating with another I2C device and ignores the communication until the next START condition is sent. Memory address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data.
DS3502
The memory address is always the second byte transmitted during a write operation following the slave address byte.
I2C Communication Writing a single byte to a slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave's acknowledgment during all byte write operations. When writing to the DS3502, the potentiometer adjusts to the new setting once it has acknowledged the new data that is being written, and the EEPROM is written following the STOP condition at the end of the write command. To change the setting without changing the EEPROM, terminate the write with a repeated START condition before the next STOP condition occurs. Using a repeated START condition prevents the tW delay required for the EEPROM write cycle to finish. Acknowledge polling: Any time a EEPROM byte is written, the DS3502 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3502, which allows communication to continue as soon as the DS3502 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM write cycles: The DS3502's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room temperature. Writing to the WR/IVR register with MODE = 1 does not count as a EEPROM write. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location.
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High-Voltage, NV, I2C POT DS3502
TYPICAL I2C WRITE TRANSACTION MSB START 0 1 0 1 0 A1 A0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER ADDRESS *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE CONNECTED TO GND). 50h A) SINGLE-BYTE WRITE REGISTER 00h 00h SLAVE ACK DATA SLAVE ACK 51h REPEATED START 0 1 0 1 0 0 0 1 SLAVE ACK DATA MASTER NACK STOP STOP
START 0 1 0 1 0 0 0 0 SLAVE 0 0 0 0 0 0 0 0 ACK 50h 02h
B) SINGLE-BYTE READ -READ CR REGISTER
START 0 1 0 1 0 0 0 0 SLAVE 0 0 0 0 0 0 1 0 SLAVE ACK ACK
Figure 3. I2C Communication Examples
Manipulating the address counter for reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. See Figure 3 for a read example using the repeated START condition to specify the starting memory location.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3502, decouple both the power-supply pin (V CC) and the wiper-bias voltage pin (V+) with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate highfrequency response for decoupling applications.
SDA and SCL Pullup Resistors
SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver must be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I2C AC Electrical Characteristics are within specification. A typical value for the pullup resistors is 4.7k.
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High-Voltage, NV, I2C POT DS3502
Typical Operating Circuit
R1 GATE 1 TFT G1 B1
CSTOR
CLCD
GATE 2
GATE 3
VCOM 2.5V 15.0V
I2 C
SDA SCL A0 A1
VCC
V+
RH RW
DS3502
GND RL
Pin Configuration
TOP VIEW
SDA GND VCC A1 A0 1 2 3 4 5 10 SCL 9 V+ RL RW RH
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE 10 SOP DOCUMENT NO. 21-0061
DS3502
8 7 6
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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